Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material in trenches etched into the dielectric layers. In an integrated circuit multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
The filling of a conductive material into features such as vias, trenches, pads or contacts, can be carried out by electrodeposition. In electrodeposition or electroplating method, a conductive material, such as copper is deposited over the substrate surface including into such features. Then, a material removal technique is employed to planarize and remove the excess metal from the top surface, leaving conductors only in the features or cavities. The standard material removal technique that is most commonly used for this purpose is chemical mechanical polishing (CMP). Chemical etching and electropolishing, which is also referred to as electroetching or electrochemical etching, are also attractive process options that are being evaluated for this application. Copper is the material of choice, at this time, for interconnect applications because of its low resistivity and good electromigration properties. Therefore, the present invention will be described for the electropolishing of copper and copper alloy layers as an example, although electropolishing of other materials such as Pt, Co, Ni etc., can also be achieved using the method and apparatus of this invention.
Standard electroplating techniques yield copper layers that deposit conformally over large features, such as features with widths larger than a few micrometers. This results in a plated wafer surface topography that is not flat. FIG. 1A shows a workpiece surface 100 with an exemplary via 102 and an exemplary trench 104 coated with conductor 106 using standard electroplating technique. As can be seen from this figure, although the surface of the conductor 106 may be flat over the small via 102, the surface of the conductor 106 over the larger trench 104 has a step “S”. During the excess conductor or overburden removal process step employing CMP, etching or electroetching, this non-flat surface topography needs to be planarized as the excess conductor is removed from the surface leaving it only within the features. If planarization is not achieved, as the thickness of the conductor is reduced, presence of the step S causes loss of conductor from within the large trench. Dashed lines 110 and 112 schematically show how conductor loss from the trench may increase from an amount “d” to a larger amount “D” as the excess conductor thickness on the surface is reduced from “t” to nearly zero, respectively. As can be appreciated, such conductor loss from within features is not acceptable.
CMP techniques have been developed to provide the capability of planarizing and at the same time removing the excess conductor layers. This is shown in FIG. 1B as dashed lines of 120 and 122. After excess conductor removal, the resulting surface is ideally planar as indicated by dashed line 122, and both the via 102 and the trench 104 are completely filled with the conductor. It should be noted that any remaining part of the excess conductor along with any other conductor layer (such as a barrier layer) are all removed to assure electrical isolation between the conductors within features 102 and 104.
Planarization capability of standard electroetching techniques is not as good as CMP. Therefore, results from these processes may lie somewhere between the cases shown in FIGS. 1A and 1B. Planarization capability of electroetching may be increased and the ideal result shown as dashed line 122 in FIG. 1B may be approached by employing a planarization pad or workpiece surface influencing device (WSID) which introduces mechanical action on the wafer surface as the conductor removal from the workpiece surface is performed. This way it may be possible to planarize the non-planar or non-flat copper surface as the excess copper is removed. Since there is mechanical action in such processes they are referred to as Electrochemical Mechanical Etching (ECME) or Electrochemical Mechanical Polishing. As the name suggest, in such approaches, electroetching is carried out as the wafer surface is contacted by a planarization pad and relative motion is established between the wafer surface and the planarization pad.
As described above, standard electroplating techniques yield conformal deposits and non-planar workpiece surfaces that need to be planarized during the excess material removal step. Newly developed electrodeposition techniques, which are collectively called Electrochemical Mechanical Deposition (ECMD) methods, utilize a pad or WSID in close proximity of the wafer surface during conductor deposition. Action of the WSID during plating gives planar deposits with flat surface topography even over the largest features present on the workpiece surface. Such a planar deposit is shown as layer 130 in FIG. 1C. Removal of excess conductive material, such as copper from such planar deposits does not require further planarization during the material removal step. Therefore, CMP, electroetching, chemical etching, electrochemical mechanical etching and chemical mechanical etching techniques may all be successfully employed for removing the overburden in a planar and uniform manner in this case.
There are several patents and patent applications describing the electroetching process carried out with the assistance of the mechanical action provided by a pad or WSID. Details of such processes are given in the following patents and patent applications: U.S. Pat. No. 6,402,925; U.S. application Ser. No. 10/238,665, entitled “Method and Apparatus for Electro-Chemical Mechanical Deposition,” filed Sep. 9, 2002 now U.S. Pat. No. 6,902,659; U.S. application Ser. No. 09/671,800, entitled “Process to Minimize and/or Eliminate Conductive Material Coating over the Top Surface of a Patterned Substrate and Layer Structure Made Thereby,” filed Sep. 28, 2000; U.S. application Ser. No. 09/841,622, entitled “Electroetching Process and System,” filed Apr. 23, 2001, now U.S. Pat. No. 6,852,630; U.S. application Ser. No. 10/201,604, entitled “Multi Step Electrodeposition Process for Reducing Defects and Minimizing Film Thickness,” filed Jul. 22, 2002, now U.S. Pat. No. 6,946,066; and U.S. Provisional Application Ser. No. 60/362,513, filed Sep. 1, 2003, entitled “Method and Apparatus for Planar Material Removal Technique Using Multi-Phase Process Environment,” filed Mar. 6, 2002.
During the standard electrodeposition and electroetching processes, workpiece or wafer is typically contacted on its front surface near its edge, all around its circumference. The conventional way of contacting the wafer involves a clamp-ring design where electrical contacts such as spring-loaded metallic fingers are pressed against the edge of the surface along the perimeter of the wafer. Contacts are protected from the process solution using seals such as O-rings or lip seals that are pushed against the wafer surface at the edge. Advance of low-k material usage in wafer processing, however, is bringing new restrictions to the use of such contacts. Low-k materials are relatively soft and mechanically weak. Pressing metallic contacts and seals against conductive films deposited on low-k materials causes damage to such materials and may even cause loss of electrical contact since the conductive film over the damaged low-k layer may itself become discontinuous. To address this challenge, a new method for forming an electrical contact to a wafer edge has been disclosed in U.S. Pat. Nos. 6,471,847 and 6,251,235, which are commonly owned by the assignee of the present invention. In this approach there is no metallic contact touching the wafer. Electrical contact is achieved using a liquid conductor, which is confined within a chamber.
Review of the above mentioned art related to Electrochemical Mechanical Etching and Electrochemical Mechanical Deposition techniques will reveal that these methods have the capability to electrotreat, i.e., electrodeposit as well as electropolish, full surface of the wafer without any need to set aside a “contacting region” protected from the process solution, such as the edge surface region that would be under a clamp-ring in an apparatus that uses electrical contacts with a clamp-ring design.
Contact designs that allow full-face electrodeposition or electroetching have been described in the following U.S. patent applications: U.S. application Ser. No. 09/685,934, entitled “Device Providing Electrical Contact to the Surface of a Semiconductor Workpiece During Metal Plating,” filed Oct. 11, 2000, now U.S. Pat. No. 6,497,800; U.S. application Ser. No. 09/735,546, entitled “Method of and Apparatus for Making Electrical Contact to Wafer Surface for Full-Face Electroplating or Electropolishing,” filed Dec. 14, 2000, now U.S. Pat. No. 6,482,307; and U.S. application Ser. No. 09/760,757, entitled “Method and Apparatus for Electrodeposition of Uniform Film with Minimal Edge Exclusion on Substrate,” filed Jan. 17, 2001, now U.S. Pat. No. 6,610,190, all commonly owned by the assignee of the present invention. As described in these applications, one method of making electrical contact to the workpiece surface involves physically touching the conductive surface of the workpiece by conductive contact elements, such as wires, fingers, springs, rollers, brushes etc., and establishing a relative motion between the contact elements and the wafer surface so that different sections of the wafer surface is physically and electrically contacted at different times. In another method, electrical contact to the workpiece surface is achieved without physically touching the wafer by the conductive contact elements. Either way, electrical contacts may be made substantially all over the surface of the wafer or only at the edge region of the wafer.
Although much progress has been made in electropolishing approaches and apparatus including contacting means of the workpiece during electropolishing, there is still need for alternative contacting means and electroetching techniques that uniformly remove excess conductive films from workpiece surfaces without causing damage and defects especially on advanced wafers with low-k materials.